View DS2164Q_4477625.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DS2164Q g.726 adpcm processor DS2164Q 022698 1/17 features ? compresses/expands 64kbps pcm voice to/from either 32kbps, 24kbps, or 16kbps as per the ccitt/ itu g.726 specification ? dual, fully independent channel architecture; device can be programmed to perform either: two expansions two compressions one expansion and one compression ? interconnects directly to combo-codec devices ? input to output delay is less than 375 m s ? simple serial port used to configure the device ? onboard time slot assigner circuit (tsac) function allows data to be input/output at various time slots ? supports channel associated signaling ? each channel can be independently idled or placed into bypass ? available hardware mode requires no host processor; ideal for voice storage applications ? backward-compatible with the ds2165 adpcm processor chip ? single +5v supply; low-power cmos technology ? available in 28-pin plcc pin assignment 27 28 26 432 5 6 7 8 9 12 13 14 15 16 17 18 25 24 23 22 21 20 19 10 11 fsy yout cs sclk sdi xout nc nc a0 a1 a2 a3 a4 a5 1 tm1 rst nc vdd yin clkx xin fsx sps mclk vss tm0 nc clky 28-pin plcc description the DS2164Q adpcm processor chip is a dedicated digital signal processing (dsp) chip that has been opti- mized to perform adaptive differential pulse code mod- ulation (adpcm) speech compression at three different rates. the chip can be programmed to compress (ex- pand) 64kbps voice data down to (up from) either 32kbps, 24kbps, or 16kbps. the compression follows the algorithm specified by ccitt recommendation g.726. the DS2164Q can switch compression algo- rithms on-the-fly. this allows the user to make maxi- mum use of the available bandwidth on a dynamic ba- sis. overview the DS2164Q contains three major functional blocks: a high performance (10 mips) dsp engine, two indepen- dent pcm interfaces (x and y) which connect directly to serial time division multiplexed (tdm) backplanes, and a serial port that can configure the device on-the-fly via an external controller. a 10 mhz master clock is re- quired by the dsp engine. the DS2164Q can be confi- gured to perform either two expansions, two compres- sions, or one expansion and one compression. the pcm/adpcm data interfaces support data rates from 256 khz to 4.096 mhz. typically, the pcm data rates
DS2164Q 022698 2/17 will be 1.544 mhz for m -law and 2.048 mhz for a-law. each channel on the device samples the serial input pcm or adpcm bit stream during a user-programmed input time slot, processes the data and outputs the re- sult during a user-programmed output time slot. each pcm interface has a control register which speci- fies functional characteristics (compress, expand, by- pass, and idle), data format ( m -law or a-law), and algo- rithm reset control. with the sps pin strapped high, the software mode is enabled and the serial port can be used to configure the device. in this mode, a novel ad- dressing scheme allows multiple devices to share a common 3-wire control bus, simplifying system-level in- terconnect. with sps low, the hardware mode is enabled. this mode disables the serial port and maps certain control register bits to some of the address and serial port pins. under the hardware mode, no external host controller is required and all pcm/adpcm input and output time slots default to time slot 0. hardware reset rst allows the user to reset both channel algorithms and the contents of the internal registers. this pin must be held low for at least 1 ms on system power-up after the master clock is stable to ensure that that the device has initialized properly. rst should also be asserted when changing to or from the hardware mode. rst clears all bits of the control register for both channels except the ipd bits; the ipd bits for both channels are set to 1. software mode tying sps high enables the software mode. in this mode, an external host controller writes configuration data to the DS2164Q via the serial port through inputs sclk, sdi, and cs . (see figure 2.) each write to the DS2164Q is either a 2-byte write or a 4-byte write. a 2- byte write consists of the address/command byte (acb), followed by a byte to configure the control reg- ister (cr) for either the x or y channel. the 4-byte write consists of the acb, followed by a byte to configure the cr, and then one byte to set the input time slot and another byte to set the output time slot. address/command byte in the software mode, the address/command byte is the first byte written to the serial port; it identifies which of the 64 possible adpcm processors sharing the port wiring is to be updated. address data must match that at inputs a0 to a5. if no match occurs, the device ignores the following configuration data. if an address match oc- curs, the next three bytes written are accepted as con- trol, input and output time slot data. bit acb.6 deter- mines which side (x or y) of the device is to be updated. the pcm and adpcm outputs are tristated during reg- ister updates. control register the control register establishes idle, algorithm reset, bypass, data format and channel coding for the selected channel. the x and y side pcm interfaces can be independently disabled (output 3-stated) via ipd. when ipd is set for both channels, the device enters a low-power standby mode. in this mode, the serial port must not be operated faster than 39 khz. alrst resets the algorithm coefficients for the selected channel to their initial values. alrst will be cleared by the device when the algorithm reset is complete.
DS2164Q 022698 3/17 pin description table 1 pin symbol type description 2 rst i reset. a high-low-high transition resets the algorithm. the device should be reset on power up and when changing to or from the hardware mode. 3 4 tm0 tm1 i test modes 0 and 1. tie to v ss for normal operation. 6 7 8 9 10 11 a0 a1 a2 a3 a4 a5 i address select. a0 = lsb; a5 = msb must match address/command word to enable the serial port. 12 sps i serial port select. tie to v dd to select the serial port; tie to v ss to select the hardware mode. 13 mclk i master clock. 10 mhz clock for the adpcm processing engine; may be asynchronous to sclk, clkx, and clky. 14 v ss signal ground. 0.0 volts. 16 xin i x data in. sampled on falling edge of clkx during selected time slots. 17 clkx i x data clock. data clock for the x side pcm interface; must be synchro- nous with fsx. 18 fsx i x frame sync. 8 khz frame sync for the x side pcm interface. 20 xout o x data output. updated on rising edge of clkx during selected time slots. 21 sclk i serial data clock. used to write to the serial port registers. 22 sdi i serial data in. data for onboard control registers; sampled on the rising edge of sclk. lsb sent first. 23 cs i chip select. must be low to write to the serial port. 24 yout o y data output. updated on rising edge of clky during selected time slots. 25 fsy i y frame sync. 8 khz frame sync for the y side pcm interface. 26 clky i y data clock. data clock for the y side pcm interface; must be synchro- nous with fsy. 27 yin i y data in. sampled on falling edge of clky during selected time slots. 28 v dd positive supply. 5.0 volts.
DS2164Q 022698 4/17 DS2164Q block diagram figure 1 x side pcm/adpcm data interface serial port control/ hardware mode logic y side pcm/adpcm data interface reset and test logic adpcm processing engine mclk v dd v ss fsx clkx xin xout sclk sps cs sdi a0 - a5 fsy clky yin yout rst tm0 tm1 serial port write figure 2 a0 a1 a2 a3 a4 a5 x/y 0 cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 address/command control note: 1. a 2-byte write is shown. the bypass feature is enabled when byp is set and ipd is cleared. during bypass, no expansion or compres- sion occurs. bypass operates on bytewide (8 bits) slots when cp/ex is set and on nibble-wide (4 bits) slots when cp/ex is cleared. a-law (u/a = 0) and m -law (u/a = 1) pcm coding is inde- pendently selected for the x and y channels via cr.2. if byp and ipd are cleared, then cp/ex determines if the input data is to be compressed or expanded.
DS2164Q 022698 5/17 address/command byte figure 3 (msb) (lsb) x/y a5 a4 a3 a2 a1 a0 symbol position name and description acb.7 reserved; must be 0 for proper operation x/y acb. 6 x/y channel select 0 = update channel y characteristics 1 = update channel x characteristics a5 acb.5 msb of device address a4 acb.4 a3 acb.3 a2 acb.2 a1 acb.1 a0 acb.0 lsb of device address control register figure 4 (msb) (lsb) as0 as1 ipd alrst byp u/a as2 cp/ex symbol position name and description as0 cr.7 algorithm select 0. see table 2. as1 cr.6 algorithm select 1. see table 2. ipd cr.5 idle and power down. 0 = channel enabled 1 = channel disabled (output 3-stated) alrst cr.4 algorithm reset. 0 = normal operation 1 = reset algorithm for selected channel byp cr.3 bypass. 0 = normal operation 1 = bypass selected channel u/a cr.2 data format. 0 = a-law 1 = m -law as2 cr.1 algorithm select 2. see table 2. cp/ex cr.0 channel coding. 0 = expand (decode) selected channel 1 = compress (encode) selected channel
DS2164Q 022698 6/17 algorithm select bits table 2 algorithm selected as2 as1 as0 64kbps to/from 32kbps 0 0 0 64kbps to/from 24kbps 1 1 1 64kbps to/from 16kbps 1 0 1 input time slot register figure 5 (msb) (lsb) d5 d4 d3 d2 d1 d0 symbol position name and description - itr.7 reserved; must be 0 for proper operation. - itr.6 reserved; must be 0 for proper operation. d5 itr.5 msb of input time slot register. d4 itr.4 d3 itr.3 d2 itr.2 d1 itr.1 d0 itr.0 lsb of input time slot register. output time slot register figure 6 (msb) (lsb) d5 d4 d3 d2 d1 d0 symbol position name and description - otr.7 reserved; must be 0 for proper operation. - otr.6 reserved; must be 0 for proper operation. d5 otr.5 msb of output time slot register. d4 otr.4 d3 otr.3 d2 otr.2 d1 otr.1 d0 otr.0 lsb of output time slot register.
DS2164Q 022698 7/17 time slot assignment/organization onboard counters establish when pcm and adpcm i/o occurs. the counters are programmed via the time slot registers. time slot size (number of bits wide) is de- termined by the state of cp/ex . the number of time slots available is determined by both the state of cp/ex and u/a . (see figures 7 through 10.) for example, if the x channel is set to compress (cp/ex = 1) and it is set to expect m -law data (u/a = 1), then the input port (xin) is set up for 32 8-bit time slots and the output port (xout) is set up for 64 4-bit time slots. the time slot organiza- tion is not dependent on which algorithm has been se- lected. note: time slots are counted from the frame sync signal starting at the first rising edge of either clkx or clky after the frame sync. DS2164Q m -law pcm interface figure 7 time slot 0 time slot n time slot 0 time slot 31 msb lsb msb lsb don't care 3-state don't care 3-state clkx, clky fsx, fsy xin, yin xout, yout ... DS2164Q m -law adpcm interface figure 8 time slot 0 time slot 1 time slot n time slot 62 time slot 63 time slot 0 clkx, clky fsx, fsy xin, yin xout, yout msb lsb don't care 3-state don't care 3-state msb lsb
DS2164Q 022698 8/17 DS2164Q a-law pcm interface figure 9 ... time slot 0 time slot n time slot 0 time slot 31 msb lsb msb lsb don't care 3-state don't care 3-state clkx, clky fsx, fsy xin, yin xout, yout DS2164Q a-law adpcm interface figure 10 time slot 0 time slot 1 time slot n time slot 62 time slot 63 time slot 0 clkx, clky fsx, fsy xin, yin xout, yout msb lsb don't care 3-state don't care 3-state msb lsb
DS2164Q 022698 9/17 hardware mode the hardware mode is intended for applications that do not have an external controller available or do not re- quire the extended features offered by the serial port. tying the sps pin to v ss disables the serial port, clears all internal register bits and maps the ipd, u/a , and cp/ex bits for both channels to external bits. (see table 3.) in the hardware mode, both the input and output time slots default to time slot 0. hardware mode table 3 pin # / name reg. location name and description 4 / a0 cp/ex (channel x) channel x coding configuration 0 = expand 1 = compress 5 / a1 as0/as1/as2 (channel x & y) algorithm select (see table 5) 6 / a2 u/a (channel x) channel x data format 0 = a-law 1 = m -law 7 / a3 cp/ex (channel y) channel y coding configuration 0 = expand 1 = compress 8 / a4 as0/as1/as2 (channel x & y) algorithm select (see table 5) 9 / a5 u/a (channel y) channel y data format 0 = a-law 1 = m -law 18 / sdi ipd (channel y) channel y idle select 0 = channel active 1 = channel idle 19 / cs ipd (channel x) channel x idle select 0 = channel active 1 = channel idle notes: 1. sclk must be tied to v ss when the hardware mode is selected. 2. when both channels are idled, power consumption is significantly reduced. 3. the DS2164Q will power-up within 800 ms after either channel is returned to active from an idle state.
DS2164Q 022698 10/17 algorithm select for hardware mode table 4 algorithm configuration of a1 and a4 64kbps to/from 32kbps tie both a1 and a4 to v ss. 64kbps to/from 24kbps hold a1 and a4 low during a hardware reset; take both a1 and a4 high after the rst pin has returned high (allow 3 m s after rst returns high before taking a1 and a4 high). 64kbps to/from 16kbps tie both a1 and a4 to v dd. DS2164Q connection to codec/filter figure 11 codec/filter DS2164Q analog interface 3-wire bus from external controller vfx- vfx+ gsx vfro dx dr mclkr bclkx bclkr fsr fsx mclkx xin yout clkx clky fsy fsx tm0 tm1 xout yin mclk sps cs sclk sdi a0 a1 a2 a3 a4 a5 rst transmit data receive data 10 mhz clock address select (address=0 shown) transmit data clock receive data clock receive frame sync transmit frame sync reset circuitry (ds1231) note: suggested codec/filters tp305x national semiconductor etc505x sgsthomson microelectronics mc1455xx motorola tcm29cxx texas instruments hd44238c hitachi *other generic codec/filter devices can be substituted.
DS2164Q 022698 11/17 pcm and adpcm input/output since the organization of the input and output time slots on the DS2164Q does not depend on the algorithm se- lected, it always assumes that pcm input and output will be in 8-bit bytes and that adpcm input and output will be in 4-bit bytes. figure 12 demonstrates how the DS2164Q handles the i/o for the three different algo- rithms. in the figure, it is assumed that channel x is in the compression mode (cp/ex = 1) and channel y is in the expansion mode (cp/ex = 0). also, it is assumed that both the input and output time slots for both channels are set to 0. pcm and adpcm i/o example figure 12 clkx fsx xout (32kbps) xout (24kbps) xout (16kbps) clky fsy yin (32kbps) yin (24kbps) yin (16kbps) yout 3state msb lsb xin msb lsb msb lsb msb lsb 3-state 3-state see note 1 00 msb lsb msb lsb msb lsb msb lsb 3-state note: 1. the bit after the lsb in the 24kbps adpcm output will only be a 1 when the DS2164Q is operated in the software mode and is programmed to perform 24kbps compression; in all other configurations, it will be a 0.
DS2164Q 022698 12/17 time slot restrictions under certain conditions, the DS2164Q does contain some restrictions on the output time slots that are avail- able. these restrictions are covered in detail in a sepa- rate application note. no restrictions occur if the DS2164Q is operated in the hardware mode. input to output delay with all three compressions algorithms, the total delay, from the time the pcm data sample is captured by the DS2164Q to the time it is output, is always less than 375 m s. the exact delay is determined by the input and out- put time slots selected for each channel. channel associated signaling the DS2164Q supports channel associated signaling (cas) via its ability to automatically change from the 32kbps compression algorithm to the 24kbps algo- rithm. if the DS2164Q is configured to perform the 32kbps algorithm, then in both the hardware and soft- ware mode, it will sense the frame sync inputs (fsx and fsy) for a double wide frame sync pulse. whenever the DS2164Q receives a double wide pulse, it will automati- cally switch from the 32kbps algorithm to the 24kbps al- gorithm. switching to the 24kbps algorithm allows the user to insert signaling data into the lsb bit position of the adpcm output because this bit does not contain any useful speech information. on-the-fly algorithm selection in the software mode, the user can switch between the three available algorithms on-the-fly. that is, the DS2164Q does not need to be reset or stopped to make the change from one algorithm to another. the DS2164Q reads the control register before it starts to process each pcm or adpcm sample. if the user wishes to switch algorithms, then the control register must be updated via the serial port before the first input sample to be processed with the new algorithm arrives at either xin or yin. the pcm and acpcm outputs will tristate during register updates.
DS2164Q 022698 13/17 absolute maximum ratings* voltage on any pin relative to ground -1.0v to +7.0v operating temperature 0 c to 70 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes logic 1 v ih 2.0 v cc +0.3 v logic 0 v il -0.3 +0.8 v supply v dd 4.5 5.5 v capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 10 pf dc electrical characteristics (0 c to 70 c; v dd =5v + 10%) parameter symbol min typ max units notes active supply current i dda 20 ma 1,2 idle supply current i ddpd 1 ma 1,2,3 input leakage i i -1.0 +1.0 m a output leakage i o -1.0 +1.0 m a 4 output current (2.4v) i oh -1.0 ma output current (0.4v) i ol +4.0 ma notes: 1. clkx = clky = 1.544 mhz; mclk = 10 mhz. 2. outputs open; inputs swinging full supply levels. 3. both channels in idle mode. 4. xout and yout are 3-stated.
DS2164Q 022698 14/17 pcm interface ac electrical characteristics (0 c to 70 c; v dd =5v + 10%) parameter symbol min typ max units notes clkx, clky period t pxy 244 3906 ns 1 clkx, clky pulse width t wxyl t wxyh 100 ns clkx, clky rise fall times t rxy t fxy 10 20 ns hold time from clkx, clky to fsx, fsy t hold 0 ns 2 setup time from fsx, fsy high to clkx, clky low t sf 50 ns 2 hold time from clkx, clky low to fsx, fsy low t hf 100 ns 2 setup time for xin, yin to clkx, clky low t sd 50 ns 2 hold time for xin, yin to clkx, clky low t hd 50 ns 2 delay time from clkx, clky to valid xout, yout t dxyo 10 150 ns 3 delay time from clkx, clky to xout, yout 3-stated t dxyz 20 150 ns 2,3,4 notes: 1. maximum width of fsx and fsy is one clkx or clky period (except for signaling frames). 2. measured at v ih = 2.0v, v il = 0.8v, and 10 ns maximum rise and fall times. 3. load = 150 pf + 2 lsttl loads. 4. for lsb of pcm or adpcm byte. master clock / reset ac electrical characteristics (0 c to 70 c; v dd =5v + 10%) parameter symbol min typ max units notes mclk period t pm 100 ns 1 mclk pulse width t wmh , t wml 45 50 55 ns mclk rise/fall times t rm , t fm 10 ns rst pulse width t rst 1 ms note: 1. mclk = 10 mhz + 500 ppm
DS2164Q 022698 15/17 serial port ac electrical characteristics (0 c to 70 c; v dd =5v + 10%) parameter symbol min typ max units notes sdi to sclk set up t dc 55 ns 1 sclk to sdi hold t cdh 55 ns 1 sclk low time t cl 250 ns 1 sclk high time t ch 250 ns 1 sclk rise and fall time t r , t f 100 ns 1 cs to sclk setup t cc 50 ns 1 sclk to cs hold t cch 250 ns 1 cs inactive time t cwh 250 ns 1 sclk setup to cs falling t scc 50 ns 1 note: 1. measured at v ih = 2.0v, v il = 0.8v, and 10ns maximum rise and fall times. pcm interface ac timing diagram figure 13 clkx clky fsx fsy xin yin xout yout (msb) t dxyz t dxyo (msb) 3-state t sf t hd t sd t hf t hold t rxy t wxyh t wxyl t pxy t fxy t hf fsx fsy
DS2164Q 022698 16/17 master clock/reset ac timing diagram figure 14 mclk rst t rm t fm t rst t pm t wmh t wml serial port ac timing diagram figure 15 sclk sdi cs t cc t ch t r t f t cl t dc t cdh t cwh t cch t scc t cwh note: 1. sclk may be either high or low when cs is taken low.
DS2164Q 022698 17/17 DS2164Q g.726 adpcm processor 28-pin plcc ch1 n 1 e e1 d1 d d2 e2 e1 c a1 a2 a b l1 b1 inches dim min max a 0.165 0.180 a1 0.090 0.120 a2 0.020 b 0.026 0.033 b1 0.013 0.021 c 0.009 0.012 d 0.485 0.495 d1 0.450 0.456 d2 0.390 0.430 e 0.485 0.495 e1 0.450 0.456 e2 0.390 0.430 l1 0.060 n 28 e1 0.050 bsc ch1 0.042 0.048

▲Up To Search▲

Price & Availability of DS2164Q

	To Download DS2164Q Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .